The present invention relates to the field of electrical integrated circuit testing. More particularly, the present invention relates to a scan test interface utilized to facilitate a system level scan test architecture.
Electronic systems and circuits have made a significant contribution towards the advancement of modem society and are utilized in a number of applications to achieve advantageous results. Numerous electronic technologies such as digital computers, calculators, audio devices, video equipment, and telephone systems have facilitated increased productivity and reduced costs in analyzing and communicating data, ideas and trends in most areas of business, science, education and entertainment. Frequently, electronic systems designed to provide these results include numerous printed circuit boards (PCBs) comprising a variety of microelectronic integrated circuits (ICs). Efficient and reliable system wide testing of ICs included in an electronic system is critical in determining if a system operates properly and provides desired results.
The complexity of commonly used integrated circuits has advanced dramatically and built in self test (BIST) diagnostics capability is essential for effective circuit testing, debugging, and maintenance. Modern BIST techniques typically include the insertion of a scan test architecture in an IC to provide controllability and observability of IC components. Usually, scan test architectures include the ability to extract or insert state information to and from a number of devices within a system (e.g., a computer system) that conform to a scan testing specification. Scan testing of complex electronic systems and circuits often requires analysis of measurements taken or xe2x80x9ccapturedxe2x80x9d at numerous test points (e.g., appropriately selected circuit nodes) after the application of test vectors to stimulate certain aspects of a circuit (e.g., a NAND gate, OR gate, functional logic devices, etc.).
Scan test architectures usually include special signals that provide directions and test vectors for scan test operations. For example, an International Electrical and Electronic Engineering (IEEE) Standard 1149.1 (also referred to as Joint Task Action Group (JTAG)) boundary scan compliant architecture requires at least 4 signals to be dedicated to scan test operations. The IEEE 1149.1 standard signals are Test Data In (TDI), Test Data Out (TDO), Test Clock (TCK) and Test Mode Select (TMS). In addition JTAG IEEE 1149.1 boundary scan standard architectures often include other optional signals, such as a very common test reset (TRST) signal. Coordinating the communication of typical scan test signals (e.g., IEEE 1149.1 compliant signals) to a multitude of various destinations throughout a typical electronic system (e.g., test points, test controllers, test registers, etc.) often requires significant resources.
Traditional system level scan test architectures typically rely upon dedicated communication lines to communicate scan test signals. The dedicated scan test communication lines are often arranged in a star configuration in which scan test control signals are transmitted directly from a central controller to test points or PCB slots in the scan test system. Typically, each test point or PCB slot in a system requires a set of scan test control signals resulting in significant resources being expended on providing numerous dedicated lines for communication of scan test signals to each testing point or PCB slot. The numerous lines typically required in a star configuration also imposes significant limitations of the number of PCBs that are scanned in an individual module.
Traditional scan test systems also typically require the insertion of an external scan control PCB for system level scan control and signaling. These external scan control PCBs pose particular problems for module to module interconnect testing, often requiring additional resources to be expended designing and implementing a scan multiplexer box to direct scan operations at particular modules. Additionally, scan controller PCBs are usually difficult to physically install and remove since they are not typically part of a product design. Furthermore, a scan controller PCB is not usually controlled (e.g., reset) by an overall electronic system controller and thus causes additional problems when it is installed during normal operations.
In addition to requiring significant resources to be expended on providing numerous dedicated lines for scan test communications, traditional system level scan test architectures typically have other serious limitations and inconvenient idiosyncrasy that detract from desirable scan test control and observability functions. For example, typical system levels scan test architectures are usually limited to one scan test chain on each target PCB. This makes testing of PCBs that have scannable devices on subordinate (e.g., daughter) PCBs difficult, especially if the PCBs are reconfigured. Reconfiguring in a traditional system level scan test architecture is particularly problematic for most scan test tools because they usually require significant resources to program the software to cope with the large number of reconfiguration scenarios that are possible.
Additional difficulties are experienced in traditional system level scan test architecture systems that do not provide flexibility in scan test programming. Traditional systems often require a full reset between programming operations that resets information in scan test registers. The scan test information stored in the register is lost when the register is reset. A full reset also typically resets the state of signals on scan test chains resulting in undesirable effects on the target scannable devices. Another problem that often occurs during programming is spurious transitions on a scan chain that typically result in the logic values on the chain that complicate test vector generation. Additionally, scan operations that require one board to hold the state of a scan operation while a second board is selected for scan test operations may not be possible when the signals of subordinate scan test chains are reset during a programming operation on the second board.
What is required is a system and method that facilitates a flexibly programmable system level scan test architecture. The system and method should facilitate resets of a TAP controller without necessarily resetting other scan test registers. The system an method should also facilitate reduction of spurious transitions on a scan chain and assist one board to hold the state of a scan operation while a second board is selected for scan test operations.
Accordingly, the present invention is a scan test interface system and method that facilitates a flexibly programmable system level scan test architecture. The present invention provides a scan test signal interface between an upstream scan test device and downstream scan test devices and facilitates resets of a scan test interface TAP controller without necessarily resetting other scan test registers. A present invention scan test interface system also facilitates reduction of spurious transitions on a scan chain and assists one board to hold the state of a scan operation while a second board is selected for scan test operations.
One embodiment of a present invention includes a scan interface chip (SIC) that acts as a communication interface and supports a partial scan test interface reset and a full scan test interface reset. In one embodiment of a present invention partial scan test interface reset, a first circuit (e.g., a SIC TAP controller) included in the scan test interface is reset and a second circuit (e.g., a SIC register) is not. The full scan test interface reset includes resetting both the first and second circuit included in the scan test interface. A present invention scan test interface with a full and partial reset does not require an intervening full reset operation to occur between programming operations. One embodiment of a present invention scan test interface facilitates programming activities by holding logic levels of subordinate scan test chain signals constant when a scan test interface is placed into or enters programming mode. This permits programming to proceed without causing spurious transitions on a scan chain during programming operations.